The present invention generally relates to semiconductor processing, and in particular to a system for selective control of spacer deposition and post spacer deposition etch processes based on spacer deposition analysis.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. This may include the width and spacing of spacer materials, interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features. Since each wafer employed in semiconductor manufacturing may be different, conventional systems may require averaging values associated with spacer deposition, or may require depositing an excess amount of spacer to insure that a minimally acceptable amount of spacer is deposited. Such conventional system suffer, therefore, from not being able to adapt to the unique critical dimensions found on any individual wafer as it is being employed in semiconductor manufacture.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms a complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The electrically active regions may need to be separated from each other by insulating and/or spacing material. Conventional systems suffer from not being able to adapt processes to the individual characteristics associated with the electrically active regions on a wafer and thus yields may be less than possible.
The requirement of small features with close spacing between adjacent features requires high-resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist and an exposing source (such as optical light, x-rays, etc.) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The ability to reduce the size of computer chips is driven by lithography technology, which in turn relies upon several lithographic parameters such as spacer deposition and formation. Due to the extremely fine patterns that are exposed on the photo resist, controlling the deposition and formation of spacer materials used to separate one component on a wafer from other components are significant factors in achieving desired critical dimensions and packing densities. Thinner and more accurately measured spacer deposits facilitate achieving the higher packing densities. Due to conventional non-uniform spacer deposition and inaccurate spacer deposition monitoring techniques, spacers having a thickness greater than the minimum required may be deposited using accepted deposition processes thus reducing yields in systems employing such conventional spacer deposition.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention and it is not intended to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system that facilitates monitoring and controlling spacer deposition. Furthermore, the present invention facilitates adapting post spacer deposition etching by providing accurate spacer deposition thickness measurements. An exemplary system may employ one or more light sources arranged to project light on one or more gratings and/or spacer depositions on a wafer and one or more light sensing devices (e.g., photo detector, photo diode) for detecting light reflected by the one or more spacer depositions. The light reflected from the one or more gratings and/or spacer depositions is indicative of at least the spacer thickness, which may vary during the spacer deposition process and which may vary on various portions of a wafer upon which spacer is being deposited.
One or more spacer deposition components are arranged to correspond to a particular wafer portion. Each spacer deposition component may be responsible for depositing spacer on one or more particular wafer portions. The spacer deposition components are selectively driven by the system to deposit spacer at a desired thickness. The progress of the spacer deposition is monitored by the system by comparing the thickness of the spacer deposits on the wafer to stored values corresponding to an acceptable thickness. Different wafers and even different components within a wafer may benefit from varying spacer thickness. By monitoring the spacer thickness at the one or more wafer portions, the present invention facilitates selective control of spacer deposition. Furthermore, by monitoring the spacer thickness at the one or more wafer portions, the present invention facilitates adapting post spacer deposition etching processes based on accurate spacer thickness measurements, which in turn facilitates achieving desired critical dimensions. As a result, more optimal spacer deposition is achieved, which in turn increases desired critical dimensions and facilitates achieving higher packing densities on the wafer.
One particular aspect of the invention relates to a system for regulating spacer deposition. At least one spacer deposition component deposits spacer on a portion of a wafer. A spacer deposition component controller controls or regulates the at least one spacer deposition component. A system for directing light directs light to the portion of the wafer and collects light reflected from the portion of the wafer and a measuring system measures thickness parameters associated with the deposited spacer according to the light reflected from the portion of the wafer. A processor is operatively coupled to the measuring system and the spacer deposition controller. The processor receives the measured data associated with the deposited spacer from the measuring system, analyzes the measured data by comparing the measured data to stored acceptable spacer thickness values to determine necessary adjustments to the spacer deposition components via the spacer deposition controller in order to facilitate regulating spacer thickness on the portion of the wafer and on subsequent portions of wafers. In an alternative aspect of the present invention, once spacer deposition is substantially complete, spacer measurements are taken and are employed to compute etching parameters that can then be employed in one or more post spacer deposition processes to facilitate achieving desired critical dimensions.
Another aspect of the present invention relates to a method for regulating spacer deposition. The method includes defining a wafer as having one or more portions upon which spacer is deposited, directing light onto the one or more portions, collecting light reflected from the one or more portions and measuring the reflected light to determine spacer thickness on the portion. The method further includes using a processor to analyze the reflected light associated with the thickness of the spacer deposit by comparing the reflected light to stored spacer thickness acceptable values. A processor may then be employed to compute adjustments to be made to one or more spacer deposition components via a spacer deposition controller to regulate the thickness of spacer deposit. In an alternative aspect of the method, once spacer deposition is substantially complete, spacer measurements are employed to compute etching parameters that can then be employed in one or more post spacer deposition processes to facilitate achieving desired critical dimensions.
Still another aspect of the present invention relates to a method for regulating spacer deposition. The method includes partitioning a wafer into a plurality of grid blocks and using one or more spacer deposition components to deposit spacer on the wafer, where each spacer deposition component functionally corresponds to a respective grid block. The method further includes determining spacer thickness on the various portions of the wafer, where each portion corresponds to a respective grid block. Once the spacer thickness has been measured, the method includes employing a processor to coordinate controlling the spacer deposition components.